In Power over Ethernet (PoE) systems, the power sourcing equipment (PSE) is arranged to disconnect the power when it detects that no PD is drawing current. Particularly, the PSE is arranged to detect whether there is a predetermined minimum current being drawn for a predetermined minimum time period over a predetermined window. A PD providing this predetermined minimum current over the predetermined minimum time period is said to provide a maintain power signature (MPS). Thus, in order to keep the PSE from shutting down the port when a PD is in standby mode, the PD generates an MPS which will draw current from the PSE with a magnitude greater than the predetermined minimum current threshold. In order to reduce the power consumption during the standby mode of the PD, the MPS current drawn is modulated. For Type 1 and 2 PDs, the PSE needs to detect a current of at least 10 mA for a minimum period of 60 ms over a 360 ms window. Typically, the PD is arranged to draw 10 mA of current for 75 ms with an off time of 250 ms, called a long MPS pulse. For Type 3 and 4 PDs, the PSE needs to detect the minimum predetermined current for a minimum of 6 ms over a 326 ms window, i.e. with an off time of no more than 320 ms. Thus, in order to ensure compliance, the PD is arranged to generate MPS pulses of 7 ms with an off period of less than or equal to 310 ms, preferably with an off time of 250 ms, the 7 ms pulsed called a short MPS pulse. An MPS pulse is thus a current pulse of a predetermined duration.
FIG. 1 illustrates a high level schematic diagram of a PoE system 10, comprising: a switch/hub 20; a plurality of twisted pairs 30 constituted within a structured cable 35; and a PD 40. Switch/hub 20 comprises: a plurality of data transformers 50 and a PSE 60. PD 40 comprises: a plurality of data transformers 50; a pair of diode bridges 70; a PD interface 80 comprising an MPS circuitry 90; a capacitor C1; a DC/DC converter 100; and a load 110. MPS circuitry 90 is illustrated as a controlled current source 92 coupled to a control circuitry 95, and responsive thereto, however this is not meant to be limiting in any way. In another embodiment, MPS circuitry 90 may be constructed of a controllable resistor whose value is selected to ensure that the requirements of MPS are provided.
A data pair is coupled across the primary of each data transformer 50 in switch/hub 20 and a first end of each twisted pair 30 is coupled across the secondary of each data transformer 50 in switch/hub 20 via respective connections, listed conventionally in two groups: connections 1, 2, 3, 6; and connections 4, 5, 7 and 8. The outputs of PSE 60 are respectively connected to the center taps of the secondary windings of data transformers 50 of switch/hub 20. Structured cable 35 typically comprises 4 twisted pairs 30.
A data pair is connected across the primary winding of each data transformer 50 of PD 40 and a second end of each twisted pair 30 is connected across the secondary winding of each data transformer 50 of PD 40 via respective connections, listed conventionally in two groups: connections 1, 2, 3, 6; and connections 4, 5, 7 and 8. The center taps of the secondary windings of a first pair of data transformers 50 of PD 40 are each connected to a respective terminal of a first diode bridge 70 and the center taps of the secondary winding of a second pair of data transformers 50 of PD 40 are each connected to a respective terminal of a second diode bridge 70. A first input of PD interface 80 is coupled to a positive terminal of first and second diode bridges 70 and a second input of PD interface 80 is coupled to a negative terminal of first and second diode bridges 70. The inputs of PD interface 80, denoted terminal TR1, TR2, are coupled to respective inputs of DC/DC converter 100, with capacitor C1 and MPS circuitry 90 coupled in parallel across the inputs of PD interface 80; terminal TR1 and terminal TR2. Load 110 is coupled to PD interface 80 via DC/DC power converter 100. PD interface 80 is illustrated herein as comprising only MPS circuitry 90, however this is not meant to be limiting in any way. Particularly, PD interface 80 further comprises dedicated circuitries (not shown) for detection and classification.
In operation, as described above, MPS circuitry 90 is arranged to generate an MPS pulse which, after start up is completed, ensures that a minimum amount of current is drawn from PSE 60 for a predetermined time over a predetermined window. Typically MPS circuitry 90 is only active when load 110 is in standby mode. Control circuitry 95 of MPS circuitry 90 may receive an input from load 110 indicating that load 110 is in a standby mode, and in response control circuitry 95 regularly energizes current source 92 to generate the required MPS pulses. Due to load changes, or cross port load regulation, there may be short term changes in the voltage output by PSE 60, with durations up to 10 ms in a typical multi-port system. The current drawn by a capacitor is given as:iC=C*(dVC/dt)  EQ. 1where C is the capacitance of the capacitor and VC is the voltage thereacross. Therefore, when the voltage output by PSE 60 is fixed, VC of capacitor C1 will also be fixed and the current iC drawn by capacitor C1 will be zero. In such a case, when load 110 is idle, the only current drawn from PSE 60 will be from MPS circuitry 90. However, when the voltage output by PSE 60 changes, as described above, voltage VC of capacitor C1 will change accordingly thereby generating a current iC. When attempting to detect whether a minimum current is being drawn therefrom, PSE 60 will be detecting the combination of the current drawn by MPS circuitry 90 and current iC drawn by capacitor C1. If MPS circuitry 90 is generating a short MPS, i.e. an MPS of 6-7 ms, current iC can distort or even cancel the short MPS, in the event that they are contemporaneous, since the changes in PSE voltage due to cross-regulation can last up to 10 ms, as indicated above.